Syllabus

Introduction to Digital Signal Processing; Need of VLSI DSP algorithms. main DSP Blocks and typical DSP Algorithms. Number Representation: Fixed point Representation Floating point Representation; Binary Adders; Binary Multiplier; Binary Dividers; Floating point Arithmetic Implementation: CORDIC architectures; Multiply Accumulator unit; Computation of Special functions using MAC cells. Redundant arithmetic, redundant number representations, carry free radix 2 addition and subtraction. Hybrid radix 4 addition. Radix 2 hybrid redundant multiplication architectures, data format conversion. Redundant to non-redundant converter. Numerical strength reduction.

Bit level arithmetic structures- parallel multipliers, interleaved floor plan and bit plan based digital filters. Bit serial multipliers. Bit serial filter design and implementation. Canonic signed digit arithmetic, Distributed arithmetic.

Synchronous pipelining and clocking styles, clock skew and clock distribution in bit level pipelined VLSI designs.

Parallel FIR filters. Pipelining of FIR filters. Parallel processing. Pipelining and parallel processing for low power FIR filters. Pipeline interleaving in digital filters.

Pipelining and parallel processing for IIR filters. Low power IIR filter design using pipelining and parallel processing, Pipelined adaptive digital filters.

Systolic Array Architectures and fast convolution algorithms.

Round off noise and its computation. State variable description of digital filters, Scaling using slow-down, retiming and pipelining.