Syllabus

Computational characteristics of DSP algorithms and applications; Architectural requirements of DSPs: high throughput, low cost, low power, small code size, embedded applications. Numerical representation of signals-word length effect and its impact. Carry free adders, multiplier. Representation of digital signal processing systems: block diagrams, signal flow graphs, data-flow graphs, dependence graphs; Techniques for enhancing computational throughput: parallelism and pipelining. Introduction, Basic Architectural Features, DSP Computational Building Blocks, Bus Architecture and Memory, Data Addressing Capabilities, Address Generation Unit, Programmability, and Program Execution, Features for External Interfacing, VLIW architecture. Basic performance issues in pipelining, simple implementation of MIPS, Instruction Level Parallelism, Dynamic Scheduling, Dynamic Hardware Prediction, Memory hierarchy. Study of Fixed point and floating-point DSP architectures Analysis of basic DSP Architectures on programmable hardware. Algorithms for FIR, IIR, Lattice filter structures, architectures for real and complex fast Fourier transforms, 1D/2D Convolutions, Winograd minimal filtering algorithm. FPGA: Architecture, different subsystems, design flow for DSP system design, mapping of DSP algorithms on to FPGA. Examples of digital signal processing algorithms suitable for parallel architectures such as GPUs and multi GPUs. Interfacing: Introduction, Synchronous Serial Interface CODE, ACODEC Interface Circuit, ADC interface.